Obsidian-Knowledge-Base/X-Knowledge-Base/wiki/Note 20 Watchdog.md

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tags: [entity] type: entity topic: stm32-lower note: 20 created: 2026-07-16

updated: 2026-07-16

Note 20: Watchdog (lower/stm32/27~28)

Projects

#	Directory	Description
27	27_iwdg_test_register	IWDG test (register)
28	28_iwdg_test_hal	IWDG test (HAL)
—	(no project)	WWDG — code reference only

Code Accuracy Audit

Path Audit

Claimed Path	Actual Path	Status
stm32/27_iwdg_test_register/Hardware/IWDG/iwdg.c	27_iwdg_test_register/Hardware/IWDG/iwdg.c	✅ Correct
stm32/27_iwdg_test_register/Hardware/IWDG/iwdg.h	27_iwdg_test_register/Hardware/IWDG/iwdg.h	✅ Correct
stm32/27_iwdg_test_register/User/main.c	27_iwdg_test_register/User/main.c	✅ Correct
stm32/28_iwdg_test_hal/Core/Src/main.c	28_iwdg_test_hal/Core/Src/main.c	✅ Correct

IWDG Driver (27_iwdg_test_register/Hardware/IWDG/iwdg.c)

Claimed by Note	Actual Code	Match?
IWDG->KR = 0xCCCC (enable)	Line 14	✅ Match
IWDG->KR = 0x5555 (enable write)	Line 17	✅ Match
IWDG->PR = 4 (PR=4 → prescaler 64)	Line 20	✅ Match
IWDG->RLR = 2499	Line 23	✅ Match
IWDG->KR = 0xAAAA (refresh/feed)	Line 32	✅ Match

IWDG main.c (27_iwdg_test_register/User/main.c)

Note claims:

• IWDG_Init(), then loop with Delay_ms(3000), flag toggle, IWDG_Refresh()
• Button press introduces extra 3s delay (tests watchdog reset)

Matches actual code.

Timeout Calculation

Note states: PR=4 → divider=64, RLR=2499 → Tout = 2500 × 64 / 40000 ≈ 4s

The note's table correctly shows: | PR | Divider | Max Timeout (RLR=4095) | |---|---|---| | 100 (4) | 64 | 6.55s |

The actual timeout with RLR=2499:

CK_IWDG = LSI / (4 × 2^PR) = 40000 / (4 × 16) = 625 Hz
Tout = (RLR + 1) / CK_IWDG = 2500 / 625 = 4 seconds

⚠️ Note: The raw Joplin note shows a formula Tout = 2500 × 64 × 4 / 40000 = 16s with an erroneous extra ×4 factor. The correct timeout is 4 seconds at LSI=40KHz.

IWDG HAL (28_iwdg_test_hal)

Claimed by Note	Actual Code	Match?
MX_IWDG_Init() generated by CubeMX	Present	✅
HAL_IWDG_Refresh(&hiwdg)	Present	✅
LSI must be enabled in RCC_OscInitStruct	Present	✅

WWDG

Note describes WWDG configuration:

RCC->APB1ENR |= RCC_APB1ENR_WWDGEN;
WWDG->CFR |= WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0;  // ÷8
WWDG->CFR |= (0x50 << 0);  // window value
WWDG->CR = 0x7F;           // counter start
WWDG->CR |= WWDG_CR_WDGA;  // enable

This is reference code only — no dedicated WWDG project directory exists.

Summary

Overall Accuracy: High

Issues Found:

1. ⚠️ IWDG timeout formula in raw note has an extra ×4 factor (shows 16s, correct is 4s)
2. WWDG code is reference-only with no project directory
3. Project 27 also has Hardware/RTC/rtc.c (dependency for timing) — a detail not mentioned in the note